Component having a via and method for manufacturing it

ABSTRACT

An advantageous method and system for realizing electrically very reliable and mechanically extremely stable vias for components whose functionality is realized in a layer construction on a conductive substrate. The via (Vertical Interconnect Access), which is led to the back side of the component and which is used for the electrical contacting of functional elements realized in the layer construction, includes a connection area in the substrate that extends over the entire thickness of the substrate and is electrically insulated from the adjoining substrate by a trench-like insulating frame likewise extending over the entire substrate thickness. According to the present system, the trench-like insulating frame is filled up with an electrically insulating polymer.

FIELD OF THE INVENTION

The present invention relates to a component whose functionality isrealized in a layer construction on a conductive substrate, having atleast one via (Vertical Interconnect Access), led to the back side ofthe component, for the electrical contacting of functional elementsrealized in the layer construction. The via includes a connection areain the substrate that extends over the entire thickness of thesubstrate, and is electrically insulated from the adjoining substrate bya trench-like insulating frame likewise extending over the entiresubstrate thickness. The present invention further relates to a methodfor manufacturing a component having such a via. In addition, thepresent invention relates to a component having functional elementswhich are realized in a layer construction on a substrate, and having aconductive cap substrate on the layer construction.

BACKGROUND INFORMATION

It is believed to be understood to lead electrical contactings through awafer or a partial area of a wafer. This type of contacting is used, forexample, in the case of components which are intended for flip-chipmounting. However, vias also permit three-dimensional packaging designs,where several components are superposed vertically and contacted.Therefore, vias are gaining increasing importance.

In the European Patent Application EP 1 671 924 A2, a micromechanicalsensor element of the type indicated at the outset is discussed, whosemicromechanical structural elements are realized in a functional layerof the layer construction. They are engaging interdigital structureshaving fixed and deflectable electrodes. For the electrical connectionof these electrodes, conductor tracks are integrated into the layerconstruction between the substrate and the patterned functional layer.These conductor tracks are each in direct contact with a substrateconnection area forming a via. Each connection area is completelysurrounded by trenches which were produced in the substrate by aback-side trenching process after completion of the layer construction,and extend over the entire thickness of the substrate. These trenchesform an insulating frame which electrically insulates the connectionarea from the adjoining substrate. The insulating frame of the viasdiscussed in EP 1 671 924 A2 is filled superficially at best, andspecifically, with the material of an insulating layer which is appliedon the back side of the substrate and patterned after the back-sidetrenching process and prior to a metallization, so that themetallization is connected with the connection area.

In practice, this realization form of a via proves to be problematic intwo respects. First of all, the insulating properties of open trenchesare indefinite. For example, these properties may be impaired bycontamination during the manufacturing or dicing process or perhaps atthe location the component is used, so that the electrical reliabilityof the via suffers. Secondly, the mechanical stability of vias having anopen insulating frame is essentially a function of its geometry, i.e.,its form, depth and width. However, the mechanical stability of a viamust always satisfy the same minimum requirements for an externalcontacting by wire bonding, for example.

SUMMARY OF THE INVENTION

With the present invention, an advantageous possibility is provided forrealizing vias that are electrically very reliable and mechanicallystable for components of the type indicated at the outset.

The intended electrical reliability and mechanical stability of the viasare achieved according to the present invention by filling up thetrench-like insulating frame with an electrically insulating polymer.

According to the present invention, it was recognized, first of all,that sufficient mechanical stability of the known vias can be attainedmost easily by filling up the insulating frame. With regard to themounting of the components under discussion here, care must be takenthat to the greatest extent possible, the back side of the component isalso free of topography in the area of the vias. In addition, thefilling should be as free from shrink holes as possible in order toachieve optimal electrical insulation of the via. The fill material andfilling process are to be selected so that the area surrounding the viaalso does not become contaminated at average temperatures.

According to the present invention, it was then recognized thatelectrically insulating polymers, both because of their electrical andmechanical properties and on the basis of the methods available forfilling trenches with a high aspect ratio, are particularly well-suitedfor insulating the known vias.

Taking the inventive idea explained above as a basis, it is furthermoreproposed to realize such a via in the conductive cap substrate of asuitably furnished component, so that this component is able to becontacted via its cap.

At this point, BCB (benzocyclobutene), ALX-211 polymers of the firmAsahi, polyimides and PBO (polyphenylene-2,6-benzobisoxazole) as well astheir layer combinations can be named as especially suitable polymers.These materials may easily be applied to the back side of the substrateby spinning or spraying under vacuum conditions, in doing which,trenches such as insulating frames are gradually filled up.

These materials exhibit very good dielectric properties. Since afterhardening, they are temperature-stable and also moisture-resistant, theyare well-suited for use in the automotive field. Their use proves to beadvantageous in the course of the manufacturing process as well, sincethey allow complete filling of the isolation trenches in a manner thatis free of shrink holes, are vacuum-suitable and permit good wetting fora resist coating. In addition, these materials possess an adapted,thermally controllable viscosity.

Because of the polymer filling of the insulating frame, the via exhibitssufficient mechanical stability in all three spatial directions, whichpermits direct wire bonding on the metal-plated surface of the via. Thisis beneficial in terms of a space-saving component structure andfacilitates a compact assembly. In this connection, it additionallyproves to be advantageous that the topography of the component back sideis typically less than 1-10 μm in the area around the via.

The thermal mismatch of silicon (CTE=3*10⁻⁶K⁻¹) and a polymer(CTE=60*10⁻⁶K⁻¹) used to fill up the insulating frame has a negativeeffect on the mechanical stability of the silicon vias. In order toincrease the mechanical stability of the vias according to the presentinvention, the thermal expansion (CTE) of polymer materials may bereduced by adding suitable fillers to the polymer base material. SiO2nanoparticles or metal oxide particles are especially suitable for thispurpose. In this way, polymer materials may also be synthesized whichexhibit a negative thermal expansion in order to realize especially lowCTEs. In this context, high filling ratios and filler blends withdefined particle-size distribution as well as good workability of thecomposite material must be ensured.

In principle, components according to the present invention may berealized with vias in any form, geometry and configuration. It isespecially advantageous in terms of mechanical robustness if theinsulating frame of the via has a rounded geometry, in particular, iscylindrical. Cylindrical vias have the advantage that they have thesmallest parasitic capacitances relative to the substrate or relative toadjacent vias.

Furthermore, the mechanical stability of the via may be increased by anadditional anchoring of the polymer filling in the insulating frame. Tothat end, the insulating frame is expanded in the area of the middleand/or its base point by proportional isotropic deep-etching. The trenchgeometry resulting in the middle area and/or at the base point bringsabout a very good mechanical stress decoupling in the transition regionbetween the substrate and the layer construction. Particularly in thecase of insulating frames having a radial geometry, the mechanicalstresses are distributed uniformly in the interface between thesubstrate and the layer construction.

Using the technology described above, vias having a contact resistanceof 2-100 Ohm may be realized particularly advantageously. To that end,the substrate material may be heavily doped in the connection area.Advantageously, the via is connected to a conductor track, implementedin the layer construction, which may be realized, for example, in theform of a suitably doped and patterned polysilicon layer. In oneespecially advantageous specific embodiment of the present invention,the contact surface of the mechanical connection between the substratematerial in the connection area, thus, the via, and the buriedpolysilicon conductor track is enlarged by patterning the substratesurface in this area prior to applying the polysilicon, thus, forexample, by providing it with steps or beads. Such structures contributeadvantageously to the reinforcement, stabilization and anchoring of thefoundation or base of the via, as well.

Moreover, in one specific embodiment of the present invention, the viais connected to a metallization, applied on the back side of thecomponent, in which a terminal pad is formed for the externalcontacting. This terminal pad may be positioned directly on the verticalvia or, with the aid of a rewiring, at another location on the back sideof the component. The contact variant with rewiring offers a higherdegree of freedom in positioning the terminal pad, which, for example,may be utilized in the case of flip-chip mounting or when stackingcomponents one upon the other.

It is significant that the via concept according to the presentinvention is suitable both for pure IC components and formicromechanical components and MEMS, so long as their functionality isrealized in a layer construction on a conductive substrate, or thecomponent structure includes a conductive cap substrate in which the viais realized.

To that end, within the course of processing the front side during themanufacturing process, at least one conductor track is implemented inthe layer construction on the semiconductor substrate, and is in directcontact with a connection area in the substrate on one hand, and on theother hand, produces an electrical connection to at least one functionalelement to be realized in the layer construction. The back side of thecomponent is processed only after the completion of the layerconstruction with the functionality of the component and after cappingwith the capping substrate. Within the course of this back-sideprocessing, an insulating frame surrounding the connection area andextending over the entire substrate thickness (typically 50-300 μm) isthen produced in the substrate. According to the present invention, thistrench-like insulating frame is filled up—as completely as possible—withan electrically insulating polymer. In addition, on the back side of thecomponent, a metallization is applied which is connected to theconnection area and in which a terminal pad is formed for the externalcontacting of the component.

The joining of the semiconductor substrate and the buried conductortrack over a large area, the support of the polymer filling and the typeof polymer ensure maximum mechanical stability of the via.

In one especially advantageous method variation, the metallization isapplied on the back side of the component prior to the back-sidetrenching process, and is patterned in such a way that it forms anetching mask for the back-side trenching process. Thus, initially thepatterned metallization is used here as an extremely selective trenchmask for a high-aspect trenching process that permits precise trenchetchings for aspect ratios above 1/40. The etching of insulating framesin the case of a moderate aspect ratio of typically 1/20 may be carriedout using the familiar photoresist technique.

Since the insulating frame is not filled up until at the end of theback-side process, if no more steps are carried out at high temperature,then such high demands no longer must be placed on the thermalresistance of the filling material. This method variant is compatiblewith the familiar MEMS and CMOS processes. Since neither the trenchingprocess nor the closing of the insulating frame require high processtemperatures, components having temperature-sensitive functionalelements may also be provided later with vias as described here.

In addition, it is especially advantageous that when using this methodvariant, a large process window is available for the trench-etching ofthe insulating frame and the filling of the insulating frame, since onlymoderate feature widths are necessary, and very wide trenches, typically5-30 μm, are able to be closed using suitable filling methods.

As already described above, there are various options for developing andfurther refining the teaching of the present invention in anadvantageous manner. In this regard, reference is made on one hand tothe claims subordinate to the independent claims and, on the other hand,to the following description of two exemplary embodiments of the presentinvention with the aid of the figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a, 1 b, 1 c, 1 d, 1 e, and 1 f illustrate the manufacture of acomponent according to the present invention on the basis of schematicsectional views of the component structure in the area of a via, insuccessive stages of the manufacturing process.

FIG. 2 shows a schematic sectional view of the component thus producedin the area of a via with wire bond positioned directly on the via.

FIG. 3 a shows a schematic sectional view of a further component thusproduced in the area of a via with rewiring and

FIG. 3 b shows a top view of the connection metallization of thiscomponent.

FIG. 4 a shows a schematic sectional view of a component according tothe present invention, with conductive cap wafer in the area of a viathrough this cap wafer.

FIG. 4 b shows a top view of the plane of the buried conductor track inthe area of the via.

FIG. 5 shows a schematic sectional view of a further component accordingto the present invention, with a conductive cap wafer and connectionpossibilities on the top side and on the back side of the component.

DETAILED DESCRIPTION

The method for manufacturing a component of the type under discussionhere starts out from what may be a heavily doped semiconductor substrate100, as shown in FIG. 1 a. In the course of processing the front side,initially a dielectric layer 9 is produced on the substrate surface. Tothat end, for example, a TEOS layer is deposited or SiO2 is oxidized tohigher valency. In the course of patterning dielectric layer 9, it isopened in the areas in which a contact is to be produced to substrate100, and specifically, in the areas of a via yet to be produced and abonding frame, which are denoted by 120 and 110 in FIG. 1 a. The contactis produced with the aid of one or more conductor tracks 11. They may berealized in a polysilicon layer 11 which, for example, is deposited onpatterned dielectric layer 9 in a LPCVD process. To,improve themechanical joining between substrate 100 and polysilicon layer 11 inarea 120, prior to depositing the polysilicon, for example,concentrically running steps, so-called beads, may be etched in thisarea 120, for instance.

In the exemplary embodiment described here, polysilicon layer 11 is thenpatterned in such a way that area 120 of the via yet to be produced andarea 110 of the bonding frame remain electrically interconnected, andafter the surface of the functional layer has been planarized, anadvantageous topography is obtained. In addition, in polysilicon layer11, a contact area 130 is patterned out for a micromechanical sensorstructure yet to be produced in a sensor area 140 of the component.

FIG. 1 b shows the layer construction after one or perhaps severaldielectric layers 13, 14 have been deposited over polysiliconconductor-track layer 11, and in the course of patterning these layers13, 14, a contact opening 15 has been produced in contact area 130, thecontact opening leading to buried conductor track 11. In a familiarsurface-micromechanical process sequence, a micromechanical sensorstructure 18 was then produced in a functional layer 16 of the layerconstruction. This sensor structure 18 is connected to conductor track11 via contact opening 15. Finally, in the exemplary embodimentdescribed here, in the areas of bonding frame 110 and via 120, ametallization 17 was also applied on functional layer 16.

Metallization 17 is used as bonding metal for mounting a cap wafer 200over sensor structure 18 with the aid of eutectic bonding. However, anyother wafer bonding technique may be used for mounting cap wafer 200, aswell. As FIG. 1 c shows clearly, cap wafer 200 and sensor structure 18of the component must be aligned precisely relative to each other.

They are also electrically connected to each other by way ofeutectically bonded metallization 17. The front-side processing of thecomponent is concluded with the mounting of cap wafer 200.

Within the course of the back-side processing now following, first ofall, the back side of substrate 100 is thinned. Available methods suchas grinding, chemical etching, dry etching and/or chemical-mechanicalpolishing are utilized for that purpose. Typically, in so doing,substrate 100 is thinned to a thickness of 50 to 300 μm. The thicknessof substrate 100 is determined particularly by the mechanical stabilityaimed at for the component and the maximum possible depth of thetrenches to be produced subsequently for the vias.

The via or the insulating frame of the via must be positioned inalignment with buried conductor track 11. To that end, alignment marksare transferred to the back side of the substrate, e.g., with the aid ofinfrared alignment with respect to metallization 17 in area 120.

In the exemplary embodiment described here, a dielectric intermediatelayer 19 is now applied on the back side of the substrate and opened inmarked area 120 of via 3 to be produced. It may be a thin CVD or polymerlayer having a thickness of 100 nm to 1000 nm. This situation is shownin FIG. 1 d.

Over dielectric intermediate layer 19 thus patterned, a metal layer 5 isdeposited and patterned. Since the terminal pads for the externalcontacting of the component or of sensor structure 18 are implemented inmetal layer 5, a metal able to be wire-bonded, which may be Al, AlSi,AlCu, AlSiCu, TiN as well as other precious and semiprecious metals, isused here. In addition, metal layer 5 may be used here, together withdielectric intermediate layer 19, as mask for the subsequent anisotropictrenching process, in which insulating frame 2 for via 3 is produced insubstrate 100. Therefore, metal layer 5 is completely or at leastpartially opened over trenches 2 to be produced. If the intention is toposition the terminal pad directly on the via to be produced, metallayer 5 may be opened over the entire peripheral insulating frame.Alternatively, resist mask 22 may cover metal layer 5 and be used forpatterning dielectric intermediate layer 19 and substrate 100. However,if the intention is to carry out a rewiring, that is, if the terminalpad is to be disposed laterally with respect to the via on the substrateback side, then when patterning metal layer 5, expediently at least onerib leading outward remains as electrical connection to the terminal padsituated outside of the insulating frame. The proportions of such ribsand the process parameters for the etching and passivation steps of thetrenching process are selected in such a way that the ribs in patternedmetal layer 5 are completely undercut. Alternatively, the undercuttingmay also be carried out in a subsequent isotropic etching step.

Insulating frame 2 was produced here in a multi-step trenching process.By a combination of anisotropic and longer isotropic etching steps atdefined depth of insulating frame 2, pocket-like expansions foranchoring polymer 21 in insulating frame 2 were produced at base point20 and in middle area 24.

Etching and rounding by proportional isotropic deep etching ofdielectric layers 9, 13, 14 additionally provides an anchoring forpolymer filling 21 at base 20 of insulating frame 2, and therefore forvia 3. A resist mask 22 was used to protect the remaining metal-freesubstrate areas.

FIG. 1 e shows the component structure after the back-side trenchingprocess, and illustrates that insulating frame 2 extends over the entirethickness of substrate 100 into dielectric layer 9 or dielectric layers13, 14, which also serve as etch stop. In this manner, a connection areaof heavily doped substrate 100 is electrically isolated from theadjoining substrate material, and thus forms a via 3 which is connectedto sensor structure 18 by way of conductor track 11.

According to the present invention, insulating frame 2 is now filled upwith an electrically insulating polymer such as BCB.

To that end, a suitable polymer layer 21 is applied under vacuumconditions by spinning or spraying. In so doing, insulating frame 2 isprogressively filled up. The thickness of polymer layer 21 is selectedin such a way that the largest openings or cavities in trench 2 up to awidth of 30 μm are completely closed. Insulating frame 2 may be filledin such a way that the entire layer construction having dielectriclayers, silicon and polymer filling of the component has an adaptedthermal expansion (CTE). The stability of this polymer closure shown inFIG. 1 f increases if there are no entrapments present and if contactarea 10 between via 3, i.e., the connection area of substrate 100, andburied conductor track 100 is as large as possible. Polymer filling 21is especially well-anchored here by pocket-like expansions 20 and 24 oftrench 2.

Finally, the contact or bonding areas of via 3 are opened, e.g., byall-over backthinning of polymer layer 21 or by photopatterning in theregion of the bonding areas.

At this point, it should be noted that after filling insulating frame 2,in principle, further processing steps may also be carried out on thefront side and/or back side of the component.

As an alternative to the back-side process described above, thepossibility also exists of producing the isolation trenches prior toapplying a back-side metallization and to fill it with a polymer. Theback side of the component may then still be planarized before furtherlayers are applied to realize the terminal pads. Methods such as finegrinding or mechanical/chemical polishing may be used for theplanarization process.

FIG. 2 shows the result of the manufacturing process described above, inthe form of a component. It is an acceleration sensor element whosemicromechanical functional elements 18 have been realized in the layerconstruction on semiconductor substrate 100. Micromechanical functionalelements 18 are protected by cap wafer 200 which, for example, has beenmounted by eutectic bonding on the layer construction of the component.Micromechanical functional elements 18 are electrically contacted viaburied conductor track 11, which is electrically insulated by dielectriclayers 9 and 13, 14 from heavily doped semiconductor substrate 100 onone hand, and from functional layer 16 having functional elements 18 onthe other hand. Conductor track 11 produces a connection betweenmicromechanical functional elements 18 and a connection area 3 ofsubstrate 100, which is isolated from the adjoining substrate materialby a cylindrical insulating frame 2, and forms the via. In areas 120 and110, the base of functional layer 16 has an, at most, very low (<500 nm)topography. As a result, the metallization in this area is alsovirtually free of topography, which is a prerequisite for a hermeticallysealed eutectic bond to cap wafer 200.

According to the present invention, insulating frame 2 is filled with adielectric polymer 21. On the back side of the substrate is a patternedmetallization 5, which is in direct contact with connection area 3, butotherwise is electrically insulated from substrate 100 by a dielectriclayer 19. Terminal pad 30 for the external contacting of the component,i.e., of functional elements 18, is positioned here directly onconnection area 3 which, because of polymer filling 21, is mechanicallystabilized to the extent that a direct wire bonding 50 on via 3 ispossible, which is illustrated in FIG. 2. Metallization 5 is patternedhere in such a way that terminal pad 30 is insularly separated from theremainder of metallization 5. Metallization 5 lying outside of the padarea is used as mask for the trenching process to produce the insulatingframe. This metallization is not necessary when, because of a loweraspect ratio, a resist mask may also be used.

The same reference numerals are used in FIG. 3 a as in FIG. 2, since thetwo components shown here are identically constructed. They differ onlyin the patterning of metallization 5, that is, in the positioning of theterminal pad for the external contacting.

While in the case of FIG. 2, terminal pad 30 is positioned directly onvia 3, terminal pad 40 of the component shown in FIG. 3 a is disposed tothe side of via 3. Accordingly, wire bonding 50 is also to the side ofvia 3. In order to realize terminal pad 40 to the side of via 3, arewiring was necessary, which is illustrated by FIG. 3 b. The area ofmetallization 5 which is in direct contact with connection area 3 isstill connected here to the metallization of terminal pad 40 by way ofribs 5 a, 5 b, 5 c. In principle, only one rib is also sufficient forthe connection between via and terminal pad.

As already mentioned, the via explained in great detail above may alsobe realized within what may be a heavily doped cap wafer. An example forthis variant of the present invention is shown in FIG. 4 a.

It is likewise an acceleration sensor element whose micromechanicalfunctional elements 18 have been realized in a layer construction on asemiconductor substrate 100. Micromechanical functional elements 18 areprotected by a cap wafer 200 made of a conductive material. This capwafer 200 was bonded by a metallization 17, 17 a in areas 110 of thebonding frame and 120 of the via onto the layer construction of thecomponent. Micromechanical functional elements 18 are electricallycontacted by way of one or more buried conductor tracks 11, which areelectrically insulated by dielectric layers 9 and 13, 14 from heavilydoped semiconductor substrate 100 on one hand, and from functional layer16 on the other hand. Conductor track 11 produces a connection betweenmicromechanical functional elements 18 and a connection area 3 thatextends over functional layer 16, metallization 17 a and cap wafer 200and is insulated from the adjoining layer material by a cylindricalinsulating frame 2. According to the present invention, insulating frame2 is filled with a dielectric polymer 21.

Insulating frame 2 may be produced in a one-step trenching process aftercap wafer 200 has been bonded on. In this case, it is advisable topattern metallization 17, 17 a appropriately before cap wafer 200 isbonded on. However, insulating frame 2 may also be produced in twosteps, by already applying it in the course of patterning functionallayer 16. After the bonding process, cap wafer 200 then just merely hasto be trenched. However, this requires an alignment relative toisolation trench insulating frame 2 in functional layer 16. In bothcases, dielectric layers 9 and 13, 14 act as trench stop.

Located on cap wafer 200 is a patterned metallization 5 which is indirect contact with connection area 3, but otherwise is electricallyinsulated from cap wafer 200 by a dielectric layer 19. Terminal pad 40for the external contacting of the component or of functional elements18 is situated here to the side of via 3. To that end, a rewiring wasnecessary, as shown, for example, in FIG. 3 b.

FIG. 4 b illustrates the electrical contacting of micromechanicalfunctional elements 18 of the component shown in FIG. 4 a, in light of aschematic top view of the layer plane of conductive polysilicon layer 1,in which a buried conductor track 11 with connection to functionalelements 18 is patterned. In the present exemplary embodiment, via 3 issurrounded by an insulating frame 2 having a ring-shaped cross section.As can be seen in FIG. 4 a, insulating frame 2 extends through cap wafer200 and functional layer 16 to next underlying dielectric layer 9 or 13,14. In the area in which the base of insulating frame 2 is on dielectriclayer 9, it isolates a circular connection area 23 from polysiliconlayer 1. This connection area 23 is connected only to conductor track11. Since dielectric layers 13, 14 are superposed on this conductortrack 11, insulating frame 2 does not cut through polysilicon layer 1here, but rather ends already on dielectric layers 13, 14.

The component illustrated in FIG. 5 was furnished with two vias, namely,with a via 31 in substrate 100 as shown in FIG. 2, and with a via 32 incap wafer 200 as shown in FIG. 4 a. Therefore, reference is made here tothe description of FIGS. 2 and 4. In the case of this component, thesensor signal is able to be picked off both starting from the back sideof the component and via cap 200. For that reason, it is particularlysuitable for placement within a stack of components.

What is claimed is:
 1. A method for manufacturing a component having alayer construction, starting from a semiconductor substrate, the methodcomprising: providing at least one conductor track on the semiconductorsubstrate, the conductor track extending laterally on a surface of thesubstrate and being in direct contact with at least one connection areain the substrate; producing at least one functional element in afunctional layer provided on the conductor track, wherein the conductortrack is electrically connected to the at least one functional element;producing, after completion of the layer construction, a trench-likeinsulating frame surrounding the at least one connection area of thesubstrate and vertically extending over the entire substrate thicknessin the substrate using a back-side trenching process; fully filling upthe trench-like insulating frame with an electrically insulatingpolymer; and applying, on the back side of the component, a patternedmetallization that is connected to the connection area; and forming atleast one terminal pad; wherein the connection area is electricallyinsulated from adjacent surrounding areas of the substrate by thetrench-like insulating frame.
 2. A method for manufacturing a componenthaving a layer construction, starting from a semiconductor substrate,the method comprising: providing at least one conductor track on thesemiconductor substrate, the conductor track extending laterally on asurface of the substrate and being in direct contact with at least oneconnection area in the substrate; producing at least one functionalelement in a functional layer provided on the conductor track, whereinthe conductor track is electrically connected to the at least onefunctional element; producing, after completion of the layerconstruction, a trench-like insulating frame surrounding the at leastone connection area of the substrate and vertically extending over theentire substrate thickness in the substrate using a back-side trenchingprocess; fully filling up the trench-like insulating frame with anelectrically insulating polymer; and applying, on the back side of thecomponent, a patterned metallization that is connected to the connectionarea; and forming at least one terminal pad; wherein the connection areais electrically insulated from adjacent surrounding areas of thesubstrate by the trench-like insulating frame, and wherein themetallization is applied on the back side of the component and patternedprior to the back-side trenching process, so that the patternedmetallization forms an etching mask for the back-side trenching processsubsequently carried out.
 3. The method of claim 1, wherein theinsulating frame is expanded in at least one of a middle area and a basearea by isotropic etching.
 4. The method of claim 1, wherein the polymerfor filling the insulating frame is applied to the back side of thesubstrate by spinning or spraying under vacuum conditions.
 5. The methodof claim 1, wherein the polymer filling is planarized by fine grindingand/or by chemical-mechanical polishing.